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february 1999 preliminary ml4803 8-pin pfc and pwm controller combo 1 block diagram general description the ml4803 is a space-saving controller for power factor corrected, switched mode power supplies that offers very low start-up and operating currents. power factor correction (pfc) offers the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching fets, and results in a power supply fully compliant to iec1000-3-2 specifications. the ml4803 includes circuits for the implementation of a leading edge, average current ?boost? type pfc and a trailing edge, pwm. the ml4803-1?s pfc and pwm operate at the same frequency, 67khz. the pfc frequency of the ml4803-2 is automatically set at half that of the 134khz pwm. this higher frequency allows the user to design with smaller pwm components while maintaining the optimum operating frequency for the pfc. an overvoltage comparator shuts down the pfc section in the event of a sudden decrease in load. the pfc section also includes peak current limiting for enhanced system reliability. features internally synchronized pfc and pwm in one 8-pin ic patented one-pin voltage error amplifier with advanced input current shaping technique peak or average current, continuous boost, leading edge pfc (input current shaping technology) high efficiency trailing-edge current mode pwm low supply currents; start-up: 150a typ., operating: 2ma typ. synchronized leading and trailing edge modulation reduces ripple current in the storage capacitor between the pfc and pwm sections overvoltage, uvlo, and brownout protection pfc v cc ovp with pfc soft start i sense 3 veao 4 v dc 5 i limit 6 gnd 2 pwm out 8 pfc out 1 ? + ? + comp comp 35a 16.2v 17.5v v cc + ? comp + ? ?1v soft start pfc/pwm uvlo duty cycle limit oscillator pfc ? 67khz pwm ? 134khz v ref v ref 1.2v 26k 40k m1 r1 c1 30pf m2 m7 m3 m4 m6 pwm control logic ? + 1.5v dc i limit pfc i limit pwm comparator v cc ovp pfc off one pin error amplifier leading edge pfc trailing edge pwm + ? comp 7v + ? comp ?1 ?4 ref v cc 7 pfc control logic
ml4803 2 february 1999 pin configuration pin description pin name function 1 pfc out pfc driver output 2 gnd ground 3i sense current sense input to the pfc current limit comparator 4 veao pfc one-pin error amplifier input pin name function 5v dc pwm voltage feedback input 6i limit pwm current limit comparator input 7v cc positive supply (may require an external shunt regulator) 8 pwm out pwm driver output 1 2 3 4 8 7 6 5 pfc out gnd i sense veao pwm out v cc i limit v dc top view ml4803 8-pin pdip (p08) 8-pin soic (s08)
ml4803 3 february 1999 absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied. i cc current (average) ............................................. 40ma v cc max ............................................................... 18.3v i sense voltage .................................................. -5v to 1v voltage on any other pin ...... gnd - 0.3v to v cc + 0.3v peak pfc out current, source or sink ....................... 1a peak pwm out current, source or sink ..................... 1a pfc out, pwm out energy per cycle .................. 1.5j junction temperature .............................................. 150 c storage temperature range ..................... ? 65 c to 150 c lead temperature (soldering, 10 sec) ..................... 260 c thermal resistance ( ja ) plastic dip ..................................................... 110 c/w plastic soic ................................................... 160 c/w operating conditions temperature range ml4803cx-x ............................................. 0 c to 70 c ml4803ix-x ............................................-40 c to 85 c electrical characteristics unless otherwise specified, v cc = 15v, t a = operating temperature range (note 1) symbol parameter conditions min typ max units one-pin error amplifier veao output current t a = 25 o c, v eao = 6v 33.5 35.0 36.5 a line regulation 10v < v cc < 15v, v eao = 6v 0.1 0.3 a v cc ovp comparator threshold voltage t a = 0 o c to 70 o c 15.5 16.0 16.5 v pfc i limit comparator threshold voltage -0.9 -1 -1.15 v delay to output 150 300 ns dc i limit comparator threshold voltage 1.4 1.5 1.6 v delay to output 150 300 ns oscillator initial accuracy t a = 25 c 626774khz voltage stability 10v < v cc < 15v 1 % temperature stability 2% total variation over line and temp 60 67 74.5 khz dead time pfc only 0.3 0.45 0.65 s pfc minimum duty cycle v eao > 7.0v,i sense = -0.2v 0 % maximum duty cycle v eao < 4.0v,i sense = 0v 90 95 % output low impedance 8 15 output low voltage i out = -100ma 0.8 1.5 v i out = ? 10ma, v cc = 8v 0.7 1.5 v
ml4803 4 february 1999 electrical characteristics (continued) symbol parameter conditions min typ max units pfc (continued) output high impedance 8 15 output high voltage i out = 100ma, v cc = 15v 13.5 14.2 v rise/fall time c l = 1000pf 50 ns pwm duty cycle range ta = 0 o c to 70 o c, ml4803-2 0-43 0-47 0-50 % ta = 0 o c to 70 o c, ml4803-1 0-49.5 0-50 % output low impedance 8 15 output low voltage i out = ? 100ma 0.8 1.5 v i out = ? 10ma, v cc = 8v 0.7 1.5 v output high impedance 8 15 output high voltage i out = 100ma, v cc = 15v 13.5 14.2 v rise/fall time c l = 1000pf 50 ns supply v cc clamp voltage (v ccz )i cc = 10ma 16.7 17.5 18.3 v start-up current v cc = 11v, c l = 0 0.2 0.4 ma operating current v cc = 15v, c l = 0 2.5 4 ma undervoltage lockout threshold 11.5 12 12.5 v undervoltage lockout hysteresis 2.4 2.9 3.4 v note 1: limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
ml4803 5 february 1999 functional description the ml4803 consists of an average current mode boost power factor corrector (pfc) front end followed by a synchronized pulse width modulation (pwm) controller. it is distinguished from earlier combo controllers by its low pin count, innovative input current shaping technique, and very low start-up and operating currents. the pwm section is dedicated to peak current mode operation. it uses conventional trailing-edge modulation, while the pfc uses leading-edge modulation. this patented leading edge/ trailing edge (lete) modulation technique helps to minimize ripple current in the pfc dc buss capacitor. the ml4803 is offered in two versions. the ml4803-1 operates both pfc and pwm sections at 67khz, while the ml4803-2 operates the pwm section at twice the frequency (134khz) of the pfc. this allows the use of smaller pwm magnetics and output filter components, while minimizing switching losses in the pfc stage. in addition to power factor correction, several protection features have been built into the ml4803. these include soft start, redundant pfc over-voltage protection, peak current limiting, duty cycle limit, and under voltage lockout (uvlo). see figure 12 for a typical application. detailed pin descriptions v eao this pin provides the feedback path which forces the pfc output to regulate at the programmed value. it connects to programming resistors tied to the pfc output voltage and is shunted by the feedback compensation network. i sense this pin ties to a resistor or current sense transformer which senses the pfc input current. this signal should be negative with respect to the ic ground. it internally feeds the pulse-by-pulse current limit comparator and the current sense feedback signal. the i limit trip level is ? 1v. the i sense feedback is internally multiplied by a gain of four and compared against the internal programmed ramp to set the pfc duty cycle. the intersection of the boost inductor current downslope with the internal programming ramp determines the boost off-time. v dc this pin is typically tied to the feedback opto-collector. it is tied to the internal 5v reference through a 26k resistor and to gnd through a 40k resistor. i limit this pin is tied to the primary side pwm current sense resistor or transformer. it provides the internal pulse-by pulse-current limit for the pwm stage (which occurs at 1.5v) and the peak current mode feedback path for the current mode control of the pwm stage. the current ramp is offset internally by 1.2v and then compared against the opto feedback voltage to set the pwm duty cycle. pfc out and pwm out pfc out and pwm out are the high-current power drivers capable of directly driving the gate of a power mosfet with peak currents up to 1a. both outputs are actively held low when v cc is below the uvlo threshold level. v cc v cc is the power input connection to the ic. the v cc start- up current is 150a . the no-load i cc current is 2ma. v cc quiescent current will include both the ic biasing currents and the pfc and pwm output currents. given the operating frequency and the mosfet gate charge (qg), average pfc and pwm output currents can be calculated as i out = qg x f. the average magnetizing current required for any gate drive transformers must also be included. the v cc pin is also assumed to be proportional to the pfc output voltage. internally it is tied to the v cc ovp comparator (16.2v) providing redundant high- speed over-voltage protection (ovp) of the pfc stage. v cc also ties internally to the uvlo circuitry, enabling the ic at 12v and disabling it at 9.1v. v cc must be bypassed with a high quality ceramic bypass capacitor placed as close as possible to the ic. good bypassing is critical to the proper operation of the ml4803. v cc is typically produced by an additional winding off the boost inductor or pfc choke, providing a voltage that is proportional to the pfc output voltage. since the v cc ovp max voltage is 16.2v, an internal shunt limits v cc overvoltage to an acceptable value. an external clamp, such as shown in figure 1, is desirable but not necessary. v cc is internally clamped to 16.7v minimum, 18.3v maximum. this limits the maximum v cc that can be applied to the ic while allowing a v cc which is high figure 1. optional v cc clamp v cc gnd 1n4148 1n4148 1n5246b
ml4803 6 february 1999 ramp veao time vsw1 time ref ea ? + ? + osc dff r d q q clk u1 ramp clk u4 u3 c1 rl i4 sw2 sw1 + dc i1 i2 i3 vin l1 u2 figure 2. typical trailing edge control scheme. enough to trip the v cc ovp. the max current through this zener is 10ma. external series resistance is required in order to limit the current through this zener in the case where the v cc voltage exceeds the zener clamp level. gnd gnd is the return point for all circuits associated with this part. note: a high-quality, low impedance ground is critical to the proper operation of the ic. high frequency grounding techniques should be used. power factor correction power factor correction makes a nonlinear load look like a resistive load to the ac line. for a resistor, the current drawn from the line is in phase with, and proportional to, the line voltage. this is defined as a unity power factor is (one). a common class of nonlinear load is the input of a most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. peak-charging effect, which occurs on the input filter capacitor in such a supply, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. such a supply presents a power factor to the line of less than one (another way to state this is that it causes significant current harmonics to appear at its input). if the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the ac line and a unity power factor will be achieved. to hold the input current draw of a device drawing power from the ac line in phase with, and proportional to, the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. the pfc section of the ml4803 uses a boost-mode dc-dc converter to accomplish this. the input to the converter is the full wave rectified ac line voltage. no filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges, at twice line frequency, from zero volts to the peak value of the ac input and back to zero. by forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current that the converter draws from the power line matches the instantaneous line voltage. one of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. a commonly used value is 385vdc, to allow for a high line of 270vac rms . the other condition is that the current that the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. since the boost converter topology in the ml4803 pfc is of the current-averaging type, no slope compensation is required. leading/trailing modulation conventional pulse width modulation (pwm) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. the error amplifier output voltage is then compared with the modulating ramp. when the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned off. when the switch is on, the inductor functional description (continued)
ml4803 7 february 1999 ref ea ? + ? + osc dff r d q q clk u1 ramp clk u4 u3 c1 rl i4 sw2 sw1 + dc i1 i2 i3 vin l1 veao cmp u2 ramp veao time vsw1 time figure 3. typical leading edge control scheme. current will ramp up. the effective duty cycle of the trailing edge modulation is determined during the on time of the switch. figure 2 shows a typical trailing edge control scheme. in the case of leading edge modulation, the switch is turned off right at the leading edge of the system clock. when the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned on. the effective duty-cycle of the leading edge modulation is determined during the off time of the switch. figure 3 shows a leading edge control scheme. one of the advantages of this control technique is that it requires only one system clock. switch 1 (sw1) turns off and switch 2 (sw2) turns on at the same instant to minimize the momentary ? no-load ? period, thus lowering ripple voltage generated by the switching action. with such synchronized switching, the ripple voltage of the first stage is reduced. calculation and evaluation have shown that the 120hz component of the pfc ? s output ripple voltage can be reduced by as much as 30% using this method, substantially reducing dissipation in the high- voltage pfc capacitor. typical applications one pin error amp the ml4803 utilizes a one pin voltage error amplifier in the pfc section (veao). the error amplifier is in reality a current sink which forces 35a through the output programming resistor. the nominal voltage at the veao pin is 5v. the veao voltage range is 4 to 6v. for a 11.3m resistor chain to the boost output voltage and 5v steady state at the veao, the boost output voltage would be 400v. programming resistor value equation 1 calculates the required programming resistor value. rp vv i vv a m boost eao pgm = ? = ? = 400 50 35 113 . . ? (1) pfc voltage loop compensation the voltage-loop bandwidth must be set to less than 120hz to limit the amount of line current harmonic distortion. a typical crossover frequency is 30hz. equation 1, for simplicity, assumes that the pole capacitor dominates the error amplifier gain at the loop unity-gain frequency. equation 2 places a pole at the crossover frequency, providing 45 degrees of phase margin. equation 3 places a zero one decade prior to the pole. bode plots showing the overall gain and phase are shown in figures 5 and 6. figure 4 displays a simplified model of the voltage loop. c pin rv veaoc f comp p boost out = ? 2 2 (2) c w mvvf hz comp = 300 113 400 0 5 220 2 30 2 .. wmp cnf comp = 16 leading/trailing modulation (continued)
ml4803 8 february 1999 figure 4. voltage control loop 60 40 20 0 ? 20 ? 40 ? 60 gain (db) frequency (hz) 0.1 10 1000 1 100 power stage overall gain compensation network gain 0 50 100 150 200 phase ( o ) frequency (hz) 0.1 1 10 1000 100 power stage overall compensation network figure 5. voltage loop gain figure 6. voltage loop phase 50 40 30 20 10 0 i ramp (a) v eao (v) 02 7 5 13 6 4 ff @ ? 55 o c typ @ ? 55 o c typ @ 155 o c ss @ 155 o c typ @ room temp figure 7. internal ramp current vs. v eao r fc comp comp = 1 2 p (3) r hz nf k comp = = 1 628 30 16 330 . w c f r zero comp = 1 2 10 p (4) c hz k f zero = = 1 6 28 3 330 016 . . w m internal voltage ramp the internal ramp current source is programmed by way of the veao pin voltage. figure 7 displays the internal ramp current vs. the veao voltage. this current source is used to develop the internal ramp by charging the internal 30pf +12/ ? 10% capacitor. see figures 10 and 11. the frequency of the internal programming ramp is set internally to 67khz. pfc current sense filtering in dcm, the input current wave shaping technique used by the ml4803 could cause the input current to run away. in order for this technique to be able to operate properly under dcm, the programming ramp must meet the boost inductor current down-slope at zero amps. assuming the programming ramp is zero under light load, the off-time will be terminated once the inductor current reaches zero. subsequently the pfc gate drive is initiated, eliminating the necessary dead time needed for the dcm mode. this forces the output to run away until the v cc ovp shuts down the pfc. this situation is corrected by adding an typical applications (continued) ml4803 ml4803 i veao 35a i out v o 220f r load 667 ? 330k ? 11.3m ? 0.15f 15nf power stage compensation veao ? v eao + ?
ml4803 9 february 1999 typical applications (continued) figure 8. pfc soft start figure 9. i sense offset for light load conditions offset voltage to the current sense signal, which forces the duty cycle to zero at light loads. this offset prevents the pfc from operating in the dcm and forces pulse-skipping from ccm to no-duty, avoiding dmc operation. external filtering to the current sense signal helps to smooth out the sense signal, expanding the operating range slightly into the dcm range, but this should be done carefully, as this filtering also reduces the bandwidth of the signal feeding the pulse-by-pulse current limit signal. figure 9 displays a typical circuit for adding offset to i sense at light loads. pfc start-up and soft start during steady state operation veao draws 35a. at start- up the internal current mirror which sinks this current is defeated until v cc reaches 12v. this forces the pfc error voltage to v cc at the time that the ic is enabled. with leading edge modulation v cc on the veao pin forces zero duty on the pfc output. when selecting external compensation components and v cc supply circuits veao must not be prevented from reaching 6v prior to v cc reaching 12v in the turn-on sequence. this will guarantee that the pfc stage will enter soft-start. once v cc reaches 12v the 35a veao current sink is enabled. veao compensation components are then discharged by way of the 35a current sink until the steady state operating point is reached. see figure 8. pfc soft recovery following v cc ovp the ml4803 assumes that v cc is generated from a source that is proportional to the pfc output voltage. once that source reaches 16.2v the internal current sink tied to the veao pin is disabled just as in the soft start turn-on sequence. once disabled, the veao pin charges high by way of the external components until the pfc duty cycle goes to zero, disabling the pfc. the v cc ovp resets once the vcc discharges below 16.2v, enabling the veao current sink and discharging the veao compensation components until the steady state operating point is reached. it should be noted that, as shown in figure 8, once the veao pin exceeds 6.5v, the internal ramp is defeated. because of this, an external zener can be installed to reduce the maximum voltage to which the veao pin may rise in a shutdown condition. clamping the veao pin externally to 7.4v will reduce the time required for the veao pin to recover to its steady state value. uvlo once v cc reaches 12v both the pfc and pwm are enabled. the uvlo threshold is 9.1v providing 2.9v of hysteresis. generating v cc an internal clamp limits overvoltage to v cc . this clamp circuit ensures that the v cc ovp circuitry of the ml4803 will function properly over tolerance and temperature while protecting the part from voltage transients. this circuit allows the ml4803 to deliver 15v nominal gate drive at pwm out and pfc out, sufficient to drive low- cost igbts. it is important to limit the current through the zener to avoid overheating or destroying it. this can be done with a single resistor in series with the v cc pin, returned to a bias supply of typically 14v to 18v. the resistor value must be chosen to meet the operating current requirement of the ml4803 itself (4.0ma max) plus the current required by the two gate driver outputs. v cc ovp v cc is assumed to be a voltage proportional to the pfc output voltage, typically a bootstrap winding off the boost 0 0 200ms/div. v boost 0 v out v eao v cc 10v/div. 10v/div. 10v/div. 200v/div. 0 pfc gate c23 0.01f cr16 1n4148 r29 20k ? v cc rtn r28 20k ? r4 1k ? c16 1f c5 0.0082f r19 10k ? i sense r3 0.015 ? 3w
ml4803 10 february 1999 inductor. the v cc ovp comparator senses when this voltage exceeds 16v, and terminates the pfc output drive while disabling the veao current sink. once the veao current sink is disabled, the veao voltage will charge unabated, except for a diode clamp to v cc , reducing the pfc pulse width. once the v cc rail has decreased to below 16.2v the veao sink will be enabled, discharging external veao compensation components until the steady state voltage is reached. given that 15v on v cc corresponds to 400v on the pfc output, 16v on v cc corresponds to an ovp level of 426v. component reduction components associated with the v rms and i rms pins of a typical pfc controller such as the ml4824 have been eliminated. the pfc power limit and bandwidth does vary with line voltage. double the power can be delivered from a 220 v ac line versus a 110 v ac line. since this is a combination pfc/pwm, the power to the load is limited by the pwm stage. figure 11. ml4803 pfc control figure 10. typical peak current mode waveforms typical applications (continued) v isense v c1 ramp gate drive output c zero i sense v c1 5v v i sense gate output r comp rp v out = 400v veao 35a r1 4 + ? comp ? 4 3 c comp c 1 30pf
ml4803 11 february 1999 figure 12. typical application circuit. universal input 240w 12v dc output br1 600v 4a line neutral f1 5a 250v j1-1 j1-2 c19 4.7nf 250vac c20 4.7nf 250vac r24 470k ? 0.5w th1 10 ? 5a r3 0.15 ? 3w 102t l2 q5 q2 q4 q1 1000h r1 36 ? cr1 8a, 600v cr7 cr3 cr18 51v c26 0.01f 500v c18 4.7nf cr2 30a, 60v r36 220 ? l1 25h c29 0.01f cr2 30a 60v c2 2200f c3 1f c1 220f 450v r2 l3 36 ? cr5 16v 0.5w r22 10k ? r8 36 ? r23 10k ? r38 22 ? r30 200 ? c7 0.1f r27 20k ? 3w r26 20k ? 3w r10 0.75 ? 3w t2 t1 c23 0.01f cr4 cr11 cr10 cr12 cr9 r5 36 ? r11 150 ? q3 r4 1k ? ml4803 1 2 3 4 8 7 6 5 c15 0.015f c6 1f c5 8.2nf c28 1f c9 1f c10 2.2nf u2 4 5 1 2 2 3 1 r17 3.3k ? r6 1.2k ? c12 0.1f c25 0.01f 500v 12v j2-1 12vret j2-2 r18 1k ? u3 cr8 l2 4t cr15 1 10 3 4 r32 100 ? c27 0.01f r15 9.09k ? 7.0v r21 10k ? c14 4.7f c17 0.1f r16 2.37k ? r13 5.62m ? r7 10 ? cr16 in4148 r12 5.62m ? c4 0.47f 250vac r14 150 ? 2w r37 330 ? r9 1.5k ? c13 1nf r31 10 ? c11 1000f c21 1f c22 1f r29 20k ? r28 20k ? r19 10k ? pfc gnd i sense veao pwm v cc i limit v dc r20 510 ? r25 390k ? c8 0.15f c16 0.01f
ml4803 12 february 1999 physical dimensions inches (millimeters) seating plane 0.240 - 0.260 (6.09 - 6.60) pin 1 id 0.299 - 0.335 (7.59 - 8.50) 0.365 - 0.385 (9.27 - 9.77) 0.016 - 0.020 (0.40 - 0.51) 0.100 bsc (2.54 bsc) 0.008 - 0.012 (0.20 - 0.31) 0.015 min (0.38 min) 8 0 o - 15 o 1 0.055 - 0.065 (1.39 - 1.65) 0.170 max (4.32 max) 0.125 min (3.18 min) 0.020 min (0.51 min) (4 places) package: p08 8-pin pdip seating plane 0.148 - 0.158 (3.76 - 4.01) pin 1 id 0.228 - 0.244 (5.79 - 6.20) 0.189 - 0.199 (4.80 - 5.06) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.015 - 0.035 (0.38 - 0.89) 0.059 - 0.069 (1.49 - 1.75) 0.004 - 0.010 (0.10 - 0.26) 0.055 - 0.061 (1.40 - 1.55) 8 0.006 - 0.010 (0.15 - 0.26) 0 o - 8 o 1 0.017 - 0.027 (0.43 - 0.69) (4 places) package: s08 8-pin soic
ml4803 13 february 1999 micro linear corporation 2092 concourse drive san jose, ca 95131 tel: (408) 433-5200 fax: (408) 432-0295 www.microlinear.com ordering information part number pfc/pwm frequency temperature range package ml4803cp-1 67khz / 67khz 0 c to 70 c 8-pin pdip (p08) ml4803cs-1 67khz / 67khz 0 c to 70 c 8-pin soic (s08) ML4803IP-1 67khz / 67khz -40 c to 85 c 8-pin pdip (p08) ml4803is-1 67khz / 67khz -40 c to 85 c 8-pin soic (s08) ml4803cp-2 67khz / 134khz 0 c to 70 c 8-pin pdip (p08) ml4803cs-2 67khz / 134khz 0 c to 70 c 8-pin soic (s08) ml4803ip-2 67khz / 134khz -40 c to 85 c 8-pin pdip (p08) ml4803is-2 67khz / 134khz -40 c to 85 c 8-pin soic (s08) ? micro linear 1999. is a registered trademark of micro linear corporation. all other trademarks are the property of their respective owners. products described herein may be covered by one or more of the following u.s. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. other patents are pending. micro linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is gran ted by this document. the circuits contained in this document are offered as possible applications only. particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. the customer is urged to perform its own engineering review before deciding on a particular application. micro linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of micro linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual prop erty right. micro linear products are not designed for use in medical, life saving, or life sustaining applications. ds4803-01

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